,' X:[. ] :� - - __ - Figure 8: : ____ __ I I 1 ; � I I •• 1 *[. . ] II:] __ ___ I I I 1: I " " " " �---------------------- I I I I 1 : : ::::::: : : :::::::::::::::::::::: - __ Translation of the : switch I Process generated to directly implement each probe by merging together, with an OR operator, each input wire of a passive port.

E. J. Fischer, "Parallel Prefix Computation", J. ACM, 27, pp. J. J. J. Martin, "The Design of a Self-Timed Circuit for Distributed Mutual Exclusion," Proc. 1985 Chapel Hill Conf. VLSI, ed. J. L. Seitz, "System Timing," Chapter 7 in Mead and Conway, Introduction to VLSI Systems, Addison-Wesley, Reading MA (1980) [11] D. Warren, "Logic Programming and Compiler Writing," Soft­ ware-Practice and Experience, 10, 2 (1980) Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits David L.

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